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NCV7703B Triple Half-Bridge Driver with SPI Control
The NCV7703B is a fully protected Triple Half-Bridge Driver designed specifically for automotive and industrial motion control applications. The three half-bridge drivers have independent control. This allows for high side, low side, and H-Bridge control. H-Bridge control provides forward, reverse, brake, and high impedance states. The drivers are controlled via a standard Serial Peripheral Interface (SPI). This device is fully compatible with ON Semiconductor's NCV7708 Double Hex Driver.
Features http://onsemi.com MARKING DIAGRAM
14 14 1 SOIC-14 D2 SUFFIX CASE 751A 1 NCV7703B = Specific Device Code A = Assembly Location WL = Wafer Lot Y = Year WW = Work Week G = Pb-Free Package NCV7703BG AWLYWW
* * * * * * * * * * * * * * * * *
Ultra Low Quiescent Current in Sleep Mode, 1 mA for VS and VCC Power Supply Voltage Operation down to 5 V 3 High-Side and 3 Low-Side Drivers Connected as Half-Bridges Internal Free-Wheeling Diodes Configurable as H-Bridge Drivers 0.5 A Continuous (1 A peak) Current RDS(on) = 0.8 W (typ) 5 MHz SPI Control with Daisy Chain Capability Compliance with 5 V and 3.3 V Systems Overvoltage and Undervoltage Lockout Fault Reporting 1.4 A Overcurrent Threshold Detection with Optional Shutdown 3 A Current Limit with Auto Shutdown Overtemperature Warning and Protection Levels Internally Fused Leads in SOIC-14 Package for Better Thermal Performance ESD Protection up to 6 kV These are Pb-Free Devices
PIN CONNECTIONS
GND OUT3 VS CSB SI SCLK GND GND OUT1 OUT2 VCC EN SO GND
ORDERING INFORMATION
Device NCV7703BD2G NCV7703BD2R2G Package SOIC-14 (Pb-Free) SOIC-14 (Pb-Free) Shipping 55 Units / Rail 2500 / Tape & Reel
Typical Applications
* Automotive * Industrial * DC Motor Management
VS VS VS
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. M M OUT3
OUT1
OUT2
Figure 1. Cascaded Application
(c) Semiconductor Components Industries, LLC, 2010
April, 2010 - Rev. 0
1
Publication Order Number: NCV7703B/D
NCV7703B
VS DRIVE 1 VS Charge Pump Control Logic High-Side Driver Waveshaping VS Low-Side Driver OUT1
EN
ENABLE
OSC
clk
VS clk
VCC UVLO
Reference & Bias
Fault Detect
Channel Enable SO SI SPI SCLK CSB VS Undervoltage Lockout 16 Bit Logic and Latch Fault Waveshaping
Under-Load Overcurrent Thermal Warning/Shutdown
VS DRIVE 2 clk Channel Enable Fault VS DRIVE 3 clk Channel Enable Fault
OUT2
OUT3
VS
Overvoltage Lockout
Figure 2. Block Diagram
GND
PACKAGE PIN DESCRIPTION Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Symbol GND* OUT3 VS CSB SI SCLK GND* GND* SO EN VCC OUT2 OUT1 GND* Ground. Connect all grounds together. Half Bridge Output 3. Power Supply input for the output drivers and internal supply voltage. Chip Select Bar. Active low serial port operation. Serial Input Serial Clock Ground. Connect all grounds together. Ground. Connect all grounds together. Serial Output Enable. Logic high wakes the IC up from a sleep mode. Power supply input for internal logic. Half Bridge Output 2. Half Bridge Output 1. Ground. Connect all grounds together. Description
*Pins 1, 7, 8, and 14 are internally shorted together. It is recommended to also short these pins externally.
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NCV7703B
ENABLE
WDI
RESET Vout
NCV8518
D1* 1N4001
VBAT
D2** 22 mF Delay 120k GND 10 mF
VCC EN
VS OUT1
M OUT2 CSB SI SCLK SO GND GND GND GND OUT3
microprocessor
NCV7703B
M
GND
* D1 optional. For use where reverse battery protection is required. ** D2 optional. For use where load dump exceeds 40V.
Figure 3. Application Circuit
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+ -
Wake Up
NCV7703B
MAXIMUM RATINGS
Rating Power Supply Voltage (VS) (DC) (AC), t < 500 ms, Ivs > -2 A Output Pin OUTx (DC) (AC), t < 500 ms, IOUTx > -2 A Pin Voltage (Logic Input pins, SI, SCLK, CSB, SO, EN, VCC) Output Current (OUTx) (DC) (AC) (50 ms pulse, 1 s period) Electrostatic Discharge, Human Body Model, VS, OUT1, OUT2, OUT3 (Note 3) Electrostatic Discharge, Human Body Model, all other pins (Note 3) Electrostatic Discharge, Machine Model, VS, OUT1, OUT2, OUT3 (Note 3) Electrostatic Discharge, Machine Model, all other pins (Note 3) Electrostatic Discharge, Charge Device Model (Note 3) Operating Junction Temperature Storage Temperature Range Moisture Sensitivity Level (MAX 260C Processing) Value -0.3 to 40 -1 V -0.3 to 40 -1 -0.3 to 7 V A -1.8 to 1.8 Internally Limited 6 2 300 200 1 -40 to 150 -55 to 150 MSL3 kV kV V V kV C C - Unit V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Thermal Parameters 14 Pin Fused SOIC Package Junction-to-Lead (psi-JL8, YJL8) or Pins 1, 7, 8, 14 Junction-to-Ambient (RqJA, qJA) 1. 1-oz copper, 67 copper area, 0.062 thick FR4. 2. 1-oz copper, 645 mm2 copper area, 0.062 thick FR4. 3. This device series incorporates ESD protection and is tested by the following methods: ESD HBM tested per AEC-Q100-002 (EIA/JESD22-A114) ESD MM tested per AEC-Q100-003 (EIA/JESD22-A115) ESD CDM tested per EIA/JES D22/C101, Field Induced Charge Model mm2 Test Conditions (Typical Value) min-pad board (Note 1) 23 122 1 pad board (Note 2) 22 83 C/W C/W Unit
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NCV7703B
ELECTRICAL CHARACTERISTICS
(-40C TJ 150C, 5.5 V VS 40 V, 3 V VCC 5.25 V, EN = VCC, unless otherwise specified) Characteristic GENERAL Supply Current (VS) Sleep Mode (Note 5) VS = 13.2 V, OUTx = 0 V EN = SI = SCLK = 0 V, CSB = VCC 0 V < VCC < 5.25 V (TJ = -40C to 85C) VS = 13.2 V, OUTx = 0 V EN = SI = SCLK = 0 V, CSB = VCC 0 V < VCC < 5.25 V, TJ = 25C Supply Current (VS) Active Mode Supply Current (VCC) Sleep Mode (Note 6) Supply Current (VCC) Active Mode VCC Power-On-Reset Threshold VS Undervoltage Detection VS Overvoltage Detection Thermal Warning (Note 4) Thermal Shutdown (Note 4) Threshold VS decreasing Hysteresis Threshold VS increasing Hysteresis Threshold Hysteresis Threshold Hysteresis EN = VCC, 5.5 V < VS < 35 V No Load VCC = CSB, EN = SI = SCLK = 0 V (TJ = -40C to 85C) EN = VCC - 1.0 5.0 mA Conditions Min Typ Max Unit
-
-
2.0
- - - 2.60 4.3 100 34.0 1.5 120 - 155 - 1.05
2.0 0 1.5 2.80 4.7 - 37.5 3.5 145 30 175 30 1.20
4.0 2.5 3.0 3.00 5.1 400 40.0 5.5 170 - 195 - -
mA mA mA V V mV V C C C/C
Ratio of Thermal Shutdown to Thermal Warning temperature (Note 4) OUTPUTS Output RDS(on) (Source) Iout = -500 mA VS = 13.2 V, TJ = 25C VS = 13.2 V 8 V VS 40 V 5.5 V VS 8 V, TJ = 25C 5.5 V VS 8 V Output RDS(on) (Sink) Iout = 500 mA VS = 13.2 V, TJ = 25C VS = 13.2 V 8 V VS 40 V 5.5 V VS 8 V, TJ = 25C 5.5 V VS 8 V Source Leakage Current Sum of I(OUTx) x = 1, 2, 3 OUTx = 0 V, VS = 40 V, EN = 0 V CSB = VCC 0 V < VCC < 5.25 V Sum(I(OUTx) OUTx = 0 V, VS = 40 V, EN = 0 V CSB = VCC 0 V < VCC < 5.25 V, TJ = 25C Sum(I(OUTx)
- - - - -
0.8 - - 1.3 -
0.95 1.5 1.7 - 2.0
W W W W W
- - - - - -5.0
0.8 - - 1.3 - -
0.95 1.5 1.7 - 2.0 -
W W W W W mA
-1.0
-
-
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NCV7703B
ELECTRICAL CHARACTERISTICS
(-40C TJ 150C, 5.5 V VS 40 V, 3 V VCC 5.25 V, EN = VCC, unless otherwise specified) Characteristic OUTPUTS Sink Leakage Current OUTx = VS = 40 V, EN = 0 V CSB = VCC 0 V < VCC < 5.25 V OUTx = VS = 13.2 V, EN = 0 V CSB = VCC 0 V < VCC < 5.25 V, TJ = 25C Over Current Shutdown Threshold Current Limit Under Load Detection Threshold Source Sink Source Sink Source Sink - - 300 mA Conditions Min Typ Max Unit
-
-
10
-1.8 1.0 -5.0 2.0 -15 3.0 -
-1.4 1.4 -3.0 3.0 -7.0 7.0 0.9
-1.0 1.8 -2.0 5.0 -2.0 15 1.3
A A mA V
Power Transistor Body Diode Forward Voltage If = 500 mA 4. Thermal characteristics are not subject to production test 5. For temperatures above 85C, refer to Figure 4. 6. For temperatures above 85C, refer to Figure 5.
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NCV7703B
ELECTRICAL CHARACTERISTICS
(-40C TJ 150C, 5.5 V VS 40 V, 3 V VCC 5.25 V, EN = VCC, unless otherwise specified) Characteristic LOGIC INPUTS (EN, SI, SCLK, CSB) Input Threshold High Low Input Hysteresis Input Pulldown Current (EN, SI, SCLK) Input Pullup Current (CSB) Input Capacitance (Note 7) LOGIC OUTPUT (SO) Output High Output Low Tri-state Leakage Tri-state Input Capacitance (Note 7) TIMING SPECIFICATIONS Overcurrent Shutdown Delay Time Source Sink Current Limit Fault Delay Under Load Detection Delay Time High Side Turn On Time High Side Turn Off Time Low Side Turn On Time Low Side Turn Off Time High Side Rise Time High Side Fall Time Low Side Rise Time Low Side Fall Time NonOverlap Time NonOverlap Time 7. Not production tested. VS = 13.2 V, Rload = 25 W VS = 13.2 V, Rload = 25 W VS = 13.2 V, Rload = 25 W VS = 13.2 V, Rload = 25 W VS = 13.2 V, Rload = 25 W VS = 13.2 V, Rload = 25 W VS = 13.2 V, Rload = 25 W VS = 13.2 V, Rload = 25 W High Side Turn Off to Low Side Turn On Low Side Turn Off to High Side Turn On VS > 8 V ms 10 10 - 200 - - - - - - - - 1.0 1.0 25 25 200 350 7.5 3.0 6.5 3.0 5.0 2.0 1.0 1.0 - - 50 50 - 600 15 6.0 15 6.0 10 5.0 3.0 3.0 - - ms ms ms ms ms ms ms ms ms ms ms ms Iout = 1 mA Iout = -1.6 mA CSB = VCC, 0 V v SO v VCC CSB = VCC VCC - 1.0 - -10 - VCC - 0.7 0.2 - 10 - 0.4 10 15 V V mA pF EN = SI = SCLK = VCC CSB = 0 V %VCC - 30 100 5.0 -50 - - - 350 25 -25 10 70 - 600 50 -5 15 mV mA mA pF Conditions Min Typ Max Unit
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NCV7703B
ELECTRICAL CHARACTERISTICS
(-40C TJ 150C, 5.5 V VS 40 V, 3 V VCC 5.25 V, EN = VCC, unless otherwise specified) SERIAL PERIPHERAL INTERFACE Characteristic SCLK Frequency SCLK Clock Period Maximum Input Capacitance (Note 8) SCLK High Time SCLK Low Time SCLK Setup Time SI Setup Time SI Hold Time CSB Setup Time CSB High Time (Note 9) SO enable after CSB falling edge (Note 8) SO disable after CSB rising edge (Note 8) SO Rise Time SO Fall Time SO Valid Time (Note 8) VCC = 5 V, Cload = 40 pF VCC = 5 V, Cload = 40 pF SCLK to SO 50% Conditions VCC = 5 V VCC = 5 V VCC = 3.3 V SI, SCLK Timing Chart # (See Figure 6) - - - - 1 2 3 4 11 12 5 6 7 8 9 - - 10 Min - 200 500 - 85 85 85 85 50 50 100 100 200 - - - - - Typ - - - - - - - - - - - - - - - 10 10 20 Max 5 - - 15 - - - - - - - - - 50 50 25 25 50 Unit MHz ns pF ns ns ns ns ns ns ns ns ns ns ns ns
8. Not tested in production. 9. Minimum high time of CSB between two successive SPI commands.
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NCV7703B
7.0 VCC SLEEP CURRENT (mA) VS SLEEP CURRENT (mA) 6.0 5.0 4.0 3.0 2.0 1.0 0 -40 -20 VCC = 5.25 V 0 20 40 60 80 100 120 140 160 TJ, TEMPERATURE (C) VS = 13.2 V VCC = 0 V 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 -40 -20 0 20 40 60 80 100 120 140 160 VCC = 5.25 V
Figure 4. VS Sleep Supply Current vs. Temperature
Figure 5. VCC Sleep Supply Current vs. Temperature
TJ, TEMPERATURE (C)
Detailed SPI Timing
4
7
CSB
5
6
SCLK
3
1
2
CSB
SO
8
9
SI
12
SCLK
11 10
SO
Figure 6. SPI Timing Waveforms http://onsemi.com
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NCV7703B
TYPICAL CHARACTERISTICS
140 120 100 qJA (C/W) 80 60 40 20 0 0 100 200 300 400 500 600 700 (mm2) 800 1 oz Cu
2 oz Cu
COPPER HEAT SPREADING AREA
Figure 7. qJA vs. Copper Spreader Area, 14 Lead SON (fused leads)
1000 Cu Area = 100 mm2 1.0 oz 100 R(t) (C/W) 10 1 0.1 0.01 200 mm2 1.0 oz 300 mm2 1.0 oz 400 mm2 1.0 oz 500 mm2 1.0 oz
0.000001 0.00001
0.0001
0.001
0.01 TIME (sec)
0.1
1
10
100
1000
Figure 8. Transient Thermal Response to a Single Pulse 1 oz Copper (Log-Log)
140 120 100 R(t) (C/W) 80 60 40 20 0 0.000001 0.00001 0.0001 0.001 0.01 TIME (sec) 0.1 1 10 100 1000 Cu Area = 100 mm2 1.0 oz 200 mm2 1.0 oz 300 mm2 1.0 oz 400 mm2 1.0 oz 500 mm2 1.0 oz
Figure 9. Transient Thermal Response to a Single Pulse 1 oz Copper (Semi-Log)
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NCV7703B
SPI Communication Frame Detection
Standard 16-bit communication has been implemented to this IC to turn drivers on/off, and to report faults. (See Figure 11). The LSB (Least Significant Bit) is clocked in first.
Communication is Implemented as Follows:
1. CSB goes low to allow serial data transfer. 2. A 16 bit word is clocked (SCLK) into the SI (Serial Input) pin. 3. CSB goes high to transfer the clocked in information to the data registers. NOTE: SO is tristate when CSB is high.
Frame detection starts after the CSB falling edge and the SCLK rising edge.
Input word integrity (SI) is evaluated by the use of a frame consistency check. The word frame length is compared to an h x 16 bit acceptable word length before the data is latched into the input register. This guarantees the proper word length has been imported and allows for daisy chain operation applications. The frame length detector is enabled with the CSB falling edge and the SCLK rising edge. SCLK must be low during the CSB rising edge. The fault register is cleared with a valid frame detection. Existing faults are re-latched after the fault filter time.
Frame detection mode ends with CSB rising edge.
CSB
SCLK
SI
SRR
OUTL1 OUTH1 OUTL2 OUTH2 OUTL3 OUTH3
X
X
X
X
X
X
OCD
X
OVLO
Internal Counter 1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Valid 16 bits shown
Figure 10. Frame Detection
CSB
SI SCLK
SRR
OUTL1 OUTH1 OUTL2 OUTH2 OUTL3 OUTH3
X
X
X
X
X
X
OCD
X
OVLO
SO
TW
OUTL1 OUTH1 OUTL2 OUTH2 OUTL3 OUTH3
X
X
X
X
X
X
OLD
ULD
PSF
Figure 11. SPI Communication Frame Format
Table 1 defines the programming bits and diagnostic bits. Figure 11 displays the timing diagram associated with Table 1. Fault information is sequentially clocked out the SO pin of the NCV7703B as programming information is
clocked into the SI pin of the device. Daisy chain communication between SPI compatible IC's is possible by connection of the Serial Output pin (SO) to the input of the sequential IC (SI) (Reference the Daisy Chain Section).
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NCV7703B
Table 1. SPI BIT DESCRIPTION
Input Data Bit Number 15 Bit Description Over Voltage Lock Out Control (OVLO) Not Used Bit Status 0 = Disable 1 = Enable 14 Bit Number 15 Output Data Bit Description Power Supply Fail Signal (PSF for OVLO or UVLO) Under Load Detect Signal (ULD) Bit Status 0 = No Fault 1 = Fault 0 = No Fault 1 = Fault 13 Over Current Detection Shut Down Control (OCD) Not Used Not Used Not Used Not Used Not Used Not Used OUTH3 0 = Off 1 = On 5 OUTL3 0 = Off 1 = On 4 OUTH2 0 = Off 1 = On 3 OUTL2 0 = Off 1 = On 2 OUTH1 0 = Off 1 = On 1 OUTL1 0 = Off 1 = On 0 Status Register Reset (SRR) 0 = No Reset 1 = Reset 0 Thermal Warning (TW) 1 OUTL1 2 OUTH1 3 OUTL2 4 OUTH2 5 OUTL3 0 = Disable 1 = Enable 12 11 10 9 8 7 6 Not Used Not Used Not Used Not Used Not Used Not Used OUTH3 0 = Off 1 = On 0 = Off 1 = On 0 = Off 1 = On 0 = Off 1 = On 0 = Off 1 = On 0 = Off 1 = On 0 = Not in TW 1 = In TW 13 Over Load Detect Signal (OLD) 0 = No Fault 1 = Fault
14
12 11 10 9 8 7 6
DETAILED OPERATING DESCRIPTION
General Power Up/Down Control
The NCV7703B Triple Half Bridge Driver provides drive capability for 3 Half-Bridge configurations. Each output drive is characterized for a 500 mA load and has a typical 1.4 A surge capability. Strict adherence to integrated circuit die temperature is necessary, with a maximum die temperature of 150C. This may limit the number of drivers enabled at one time. Output drive control and fault reporting are handled via the SPI (Serial Peripheral Interface) port. An Enable function (EN) provides a low quiescent sleep current mode when the device is not being utilized. A pull down is provided on the EN, SI and SCLK inputs to ensure they default to a low state in the event of a severed input signal. A pull-up is provided on the CSB input disabling SPI communication in the event of an open CSB input.
A feature incorporated in the IC is an under voltage lockout circuit that prevents the output drivers from turning on unintentionally. VCC and VS are monitored for undervoltage conditions supporting a smooth turn-on transition. All drivers are initialized in the off (high impedance) condition, and will remain off during a VCC or VS undervoltage condition. This allows power up sequencing of VCC, and VS up to the user. Once VCC is out of UVLO, SPI communication can begin regardless of the voltage on VS. However, drivers will remain off if VS is in an undervoltage condition. Hysteresis in the UVLO circuits results in glitch free operation during power up/down.
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NCV7703B
H-Bridge Driver Configuration
The NCV7703B has the flexibility of controlling each half bridge driver independently. This allows for high side, low side and H-bridge control. H-bridge control provides forward, reverse, brake and high impedance states.
Overvoltage Clamping - Driving Inductive Loads
been exceeded for a duration greater than 200 ms, regardless of the OLD input bit status. The OUTx output bit will report a "0" indicating which driver encountered the hard short. The OLD status bit will be set and will remain set until a new SRR input SPI command is executed.
Under-Load Detection (Table 3)
Each output is internally clamped to ground and Vs by internal free wheeling diodes. The diodes have ratings that complement the FETs they protect.
Overcurrent Shutdown Threshold Detection (Table 2)
The state of input bit 13 (OCD) selects driver reaction when reaching overcurrent shutdown threshold. With a "0" for input bit 13, the OLD status bit will be set to "1" when the level exceeds the overcurrent shutdown shut-down threshold and the driver will remain on. With a "1" for input bit 13, the output driver shuts off when the overcurrent shutdown threshold is exceeded and can only be turned back on via the SPI port with a SPI command that includes an SRR = 1. Note: high currents could cause a high rise in die temperature. Devices will not be allowed to turn on if the die temperature exceeds the thermal shutdown temperature.
Current Limit Fault
The under-load detection circuit monitors the current from each output driver. A minimum load current (this is the maximum open circuit detection threshold) is required when the drivers are turned on. If the under-load detection threshold has been detected for more than the under-load delay time, the ULD bit (output bit #14) will be set to a "1". The under load bit is reset with SRR.
Overvoltage Shutdown (Table 4)
The current limit fault circuit will shut down the offending output driver when the Current Limit (Source or Sink) has
Overvoltage lockout circuitry monitors the voltage on the VS pin. The response to an overvoltage condition is selected by SPI input bit 15. PSF output bit 15 is set when a VS overvoltage condition exists. If input bit 15 (OVLO) is set to "1", all outputs will turn off during this overvoltage condition. Turn On/Off status is maintained in the logic circuitry, so that when proper input voltage level is reestablished, the programmed outputs will turn back on. The PSF output bit is reset with SRR.
Table 2. INPUT BIT 13, OVERCURRENT DETECTION SHUT DOWN CONTROL AND RESPONSE
OLD Input Bit 13 Set 0 0 0 1 1 Typical Load Current Condition IL 1.4 A 1.4 A < IL 3 A IL 3 A, for 200 ms (typ) IL 1.4 A IL > 1.4 A, for 25 ms (typ) Output Bit 13 OLD Status 0 1 (Need SRR to reset) 1 (Need SRR to reset) 0 1 (Need SRR to reset) OUTx Status Unchanged Unchanged OUTx Latched Off (Need SRR to reset) Unchanged OUTx Latched Off (Need SRR to reset)
Table 3. INPUT BIT 14, UNDER LOAD DETECTION SHUT DOWN
OUTx ULD Set 0 1 Output Data Bit 14, Under Load Detect (ULD) Status 0 1 (Need SRR to reset) OUTx Status Unchanged Unchanged
Table 4. INPUT BIT 15, OVERVOLTAGE LOCK OUT (OVLO) SHUT DOWN
OVLO Input Bit 15 0 0 1 1 VS OVLO Condition 0 1 0 1 Output Data Bit 15 Power Supply Fail (PSF) Status 0 1 (Need SRR to reset) 0 1 (Need SRR to reset) OUTx Status Unchanged Unchanged Unchanged All Outputs Shut Off (Remain off until VS is out of OVLO)
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NCV7703B
Thermal Shutdown
Three independent thermal shutdown circuits are featured (one common sensor for each HS and LS transistor pair). Each sensor has two temperature levels; Level 1, Thermal Warning sets the "TW" status bit to a 1 and would have to be reset with a command that includes the SRR after the IC cools to a temperature below Level 1. The output will remain on in this condition. If the IC temperature reaches Level 2, Over Temperature Shutdown, all drivers are latched off. It can be reset only after the part cools below the shutdown temperature, (including thermal hysteresis) with a turn-on command that includes the SRR set bit. The output data bit 0, Thermal Warning, will latch and remain set, even after cooling, and is reset by sending a SPI command to reset the status register (SRR, input 0 set to "1"). Since thermal warning precedes a thermal shutdown,
software polling of this bit will allow for load control and possible prevention of thermal shutdown conditions. Thermal warning information can be retrieved immediately without performing a complete SPI access cycle. Figure 12 below displays how this is accomplished. Bringing the CSB pin from a high to low condition immediately displays the information on the Output Data Bit 0, thermal warning, even in the absence of an SCLK signal. As the temperature of the NCV7703B changes from a condition from below the thermal warning threshold to above the thermal warning threshold, the state of the SO pin changes and this level is available immediately when the CSB goes low. A low on SO indicates there is no thermal warning, while a high indicates the IC is above the thermal warning threshold. This warning bit is reset by setting SRR to "1".
CSB
CSB
SCLK*
SCLK*
SO Tristate Level
TWH
SO
Tristate Level NTW
Thermal Warning High No Thermal Warning *SCLK can be high or low in order to maintain the thermal information on SO. Toggling SCLK will cause other output bits to shift out. TWH = Thermal Warning High NTW = No Thermal Warning
Figure 12. Access to Temperature Warning Information
Applications Drawing
Daisy Chain
The NCV7703B is capable of being setup in a daisy chain configuration with other similar devices which include additional NCV7703B devices as well as the NCV7708 Double Hex Driver. Particular attention should be focused on the fact that the first 16 bits which are clocked out of the SO pin when the CSB pin transitions from a high to a low
will be the Diagnostic Output Data. These are the bits representing the status of the IC and are detailed in the SPI Bit Description Table. Additional programming bits should be clocked in which follow the Diagnostic Output bits. Word length must be h x 16 due to the use of frame detection.
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NCV7703B
m icroprocessor
CSB
SCLK
CSB
SCLK
CSB
SCLK
CSB
SCLK
NCV7703B
NCV7703B
NCV7708B
NCV7708B
SI
SO
SI
SO
SI
SO
SI
SO
Figure 13. Daisy Chain Operation Parallel Control
A more efficient way to control multiple SPI compatible devices is to connect them in a parallel fashion and allow each device to be controlled in a multiplex mode. The diagram below shows a typical connection between the microprocessor or microcontroller and multiple SPI compatible devices. In a daisy chain configuration, the programming information for the last device in the serial string must first pass through all the previous devices. The parallel control setup eliminates that requirement, but at the cost of additional control pins from the microprocessor for each individual CSB pin for each controllable device. Serial data is only recognized by the device that is activated through its respective CSB pin.
NCV7703B SI SCLK SO microprocessor SI SCLK CSB OUT1 SO OUT2 OUT3
VS
OUTx
CSB chip1 CSB chip2 CSB chip3
OUTx NCV7703B SI SCLK CSB OUT1 SO OUT2 OUT3 GND NCV7703B SI SCLK CSB OUT1 SO OUT2 OUT3
Figure 14. Parallel Control Additional Application Setup
Figure 15. High-Side / Low-Side Application Drawing
In addition to the cascaded H-Bridge application shown in Figure 1, the NCV7703B can also be used as a high-side driver or low-side driver (Figure 15).
Any combination of H-bridge and high or low-side drivers can be designed in. This allows for flexibility in many systems.
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NCV7703B
PACKAGE DIMENSIONS
SOIC-14 CASE 751A-03 ISSUE J
-A-
14 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.
-B-
P 7 PL 0.25 (0.010)
M
B
M
1
7
G C -T-
SEATING PLANE
R X 45 _
F
D 14 PL 0.25 (0.010)
M
K TB
S
M A
S
J
SOLDERING FOOTPRINT*
7X
DIM A B C D F G J K M P R
MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50
INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019
7.04 1 0.58
14X
14X
1.52
1.27 PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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NCV7703B/D

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